The present invention relates to a high-output power device; and, more particularly, to an HF power device applicable to a power amplifier of a base station for a mobile communication system such as a cellular, a personal communication service (PCS) and an IMT (International Mobile Telecommunication)-2000 etc.
In addition, the present invention is relates to an HF power device applicable even to a mobile station based on a little watt in case that a structure of the device becomes scale-down, though it is being applied to a power amplifier of the base station for scores of or hundreds of watt.
In general, a MOSFET (Metal Oxide Silicon Field Effect Transistor) used as a power device has high input impedance in comparison with a bipolar transistor, thus a power gain is high and a gate driving circuit is very simple. Also the MOSFET is a unipolar device, thus it has a merit that there is less time delay occurring by a re-combination or an accumulation caused by a minority carrier during a turning-off of the device.
Therefore, it is presently getting gradually spread an application to a switching mode power supply, a lamp ballast and a motor driving circuit.
In such MOSFET, a DMOSFET (Double diffused MOSFET) using planar diffusion technique is generally used, and herewith, as a representatively used power device, an LDMOS (Laterally Double diffused MOS) structure is being used widely.
FIG. 1 is a structure diagram in a conventional technique.
As shown in FIG. 1, in the LDMOS based on the conventional technique, the MOSFET is made on a wafer 13 which is constructed by Pxe2x88x92 epitaxy layer 12 on P+ substrate 11. What this is different from a general MOSFET device manufacturing process is that an overall lower part of the substrate is used as common source electrode 22 by forming a P+ sinker 14 on a source side of the wafer 13 and connecting with a P+ substrate 11.
Further, in designing the device in a multi-finger shape, there is no need to connect several numbers of source electrodes with one another, to thereby enable to reduce a parasitic capacity by an overlapping of a metal wire and serve as an important role of a heat sink by a source of a wide area. Herewith, non-described reference number 15 indicates polysilicon, 16 represents tungsten silicide, 17 as a channel ion injection layer, 18 as an LDD area, 19 as N+ source and drain, 20 as a P+ enhancement layer for lessening a resistance of a P+ sinker 14, 21 as an insulation film, 22 as source electrode, and 23 indicates drain electrode.
Meantime, it is on the rise very importantly a process of forming the P+ sinker 14 in a source side.
In the conventional technique as the above, in order to form the P+ sinker 14, high energy and high concentration of ions are implanted into the source area, and this is diffused by a thickness of the Pxe2x88x92 the epitaxy layer 12 at high temperature for a long time to be connected to the P+ substrate 11. Such structure seriously causes an unnecessary lateral diffusion owing to the diffusion for a long time, thus an area of the device becomes large, and a parasitic resistance and a parasitic capacitance are increased by such result, which is an important cause of reducing an HF characteristic of the power device.
Furthermore, the conventional LDMOS structure thickly grows a field oxide film by thickness of 2 xcexcmxcx9c3 xcexcm to reduce the parasitic capacitance, that is, a high thermal anneal process is required correspondingly to the thickness of the field oxide film, and a scale-down extent of the device and a flat degree of the wafer become bad to cause a difficulty in fabricating the device.
Therefore, it is an object of the present invention to provide an HF power device and its manufacturing method, which are capable of preventing an HF characteristic of a power device from being reduced by forming a low-resistance sink through a thermal anneal process at low temperature of 1000xc2x0 C. and below, and so by restraining an area increase of the device and an increase of a parasitic resistance and a parasitic capacitance.
Another object of the present invention is to provide an HF power device and its manufacturing method for restraining a drop of a scale-down extent and a flat degree of the device in forming a field oxide film.
To achieve these and other advantages, and in accordance with the purpose of the present invention, the HF power device includes a first conductive type semiconductor layer; a field area formed by a trench structure on one side of the semiconductor layer; gate electrode formed on a given surface of the semiconductor layer; a second conductive type channel layer which is laterally diffused from the field area to a width containing both sides of the gate electrode, and formed on the surface of the semiconductor layer; a second conductive type source area formed within the channel layer between one side of the gate electrode and the field area; a second conductive type drain area formed on the surface of the semiconductor layer with a given interval from another side of the gate electrode; a first conductive type sinker, which is provided by a column shape of a trench structure for dividing into two source areas by a piercing through the source area, and is connected to the semiconductor layer; a second conductive type LDD area formed on the surface of the semiconductor layer between the drain area and the gate electrode; first metal electrode contacted with the source area divided into two source areas and electrically connected to the semiconductor layer through the sinker; and second metal electrode contacted with the drain area.
In accordance with the present invention, the method of manufacturing an HF power device includes the steps of forming a first conductive semiconductor layer on a first conductive semiconductor substrate; etching the first conductive semiconductor layer by a given depth and forming a first trench; doping first conductive impurity on the neighborhood of the first trench and forming a first conductive/first impurity layer connected to the first conductive semiconductor substrate; burying a conduction film of a first conductive type in the first trench; etching the first conductive semiconductor layer by a given depth and forming a second trench with a constant interval from the first trench; forming a field oxide film buried in the second trench; forming gate electrode on a given surface of the first conductive semiconductor layer; forming a second conductive source area on the surface of the first conductive semiconductor layer so as to be structurally self-aligned on one side of the gate electrode and be structurally pierced by the first conductive conduction film; forming a second conductive drain area on the surface of the first conductive semiconductor layer with a given distance from another side of the gate electrode; forming a second conductive/second impurity layer on the surface of the first conductive semiconductor layer between the second conductive drain area and the gate electrode; forming first metal electrode having a width which reaches the second conductive source area and the gate electrode; and forming second metal electrode electrically connected to the second conductive/second impurity layer.